Publications


Journal

  1. Shobha Vasudevan, E. A. Emerson and J. A. Abraham. Improved Verification of Hardware Designs through Antecedent Conditioned Slicing, International Journal on Software Tools and Technology Transfer (STTT), 9(1): 89-101 (2007). Invited paper, selected for journal special issue from AVOCS.
  2. Shobha Vasudevan, Vinod Viswanath, Robert Sumners and J. A. Abraham. Automatic Verification of Arithmetic Circuits in RTL Using Stepwise Refinement of Term Rewriting Systems, IEEE Transactions of Computers 56(10): 1401-1414 (2007)
  3. Shobha Vasudevan, Vinod Viswanath, J. A. Abraham, and Jiajin Tu. Sequential Equivalence Checking of System Level and RTL Descriptions, Design Automation for Embedded Systems (DAEM). 12(4): 377-396 (2008). Invited paper, selected for special journal issue from MEMOCODE.
  4. Vinod Viswanath, Shobha Vasudevan, Jacob A. Abraham: Dedicated Rewriting: Automatic Verification of Low Power Transformations in Register Transfer Level. Journal of Low Power Electronics 5(3): 339-353 (2009)
  5. Lingyi Liu, David Sheridan, William Tuohy and Shobha Vasudevan, A Technique for Test Coverage Closure Using GoldMine. IEEE Trans. on CAD of Integrated Circuits and Systems (IEEE TCAD)31(5): 790-803 (2012)
  6. Jayanand Asok Kumar and Shobha Vasudevan. Formal performance analysis for faulty MIMO hardware. IEEE Transactions on Very Large Scale Integrated Systems ( IEEE TVLSI) 20(10): 1914-1918 (2012).
  7. Jayanand Asok Kumar and Shobha Vasudevan, SHARPE: Variation-Conscious Formal Timing Analysis, IEEE Transactions on CAD of Integrated Ciruits and Systems (IEEE TCAD), 32 (5): 788-801(2013)
  8. Samuel Hertz, David Sheridan and Shobha Vasudevan. A Combination of Data Mining and Static Analysis to Automatically Infer Assertions IEEE Trans. on CAD of Integrated Circuits and Systems 31 (IEEE TCAD) 32 (6): 952-965(2013)
  9. Lingyi Liu, and Shobha Vasudevan, Automatic Generation of System Level Assertions from Transaction Level Models. Accepted. Journal of Electronic Testing: Theory and Applications (JETTA) 29(5): 669-684 (2013)
  10. Jayanand Asok Kumar, Seyed Nematollah Ahmadyan and Shobha Vasudevan, Efficient statistical model checking of hardware circuits with multiple failure regions. Accepted. To appear in IEEE Transactions on CAD of Integrated Ciruits and Systems (IEEE TCAD)
  11. Lingyi Liu and Shobha Vasudevan, Scaling Input Stimulus Generation through a Hybrid Static and Dynamic Analysis of RTL. Accepted. To appear in IEEE Transactions of Design Automation of Electronic Systems (IEEE TODAES)
  12. Shobha Vasudevan, Samuel Hertz and Lingyi Liu, A Comparative Study of Statically Guided Algorithms for Assertion Mining. Accepted. To appear in IEEE Transactions on CAD of Integrated Ciruits and Systems (IEEE TCAD)

Conference

  1. Shobha Vasudevan, E. A. Emerson and J. A. Abraham. Efficient Model Checking of Hardware using Conditioned Slicing, Automatic Verification of Critical Systems (AVOCS), 2004. Electr. Notes Theor. Comput. Sci. 128(6): 279-294 (2005)
  2. Shobha Vasudevan, Vinod Viswanath, J. A. Abraham, and Jiajin Tu. Automatic Decomposition for Sequential Equivalence Checking of System Level and RTL Descriptions, International Conference on Formal Methods and Models for Codesign (MEMOCODE) 2006: 71-80
  3. Shobha Vasudevan, Vinod Viswanath, and J. A. Abraham . Efficient Microprocessor Verification Using Antecedent Conditioned Slicing, International Conference on (VLSI Design) 2007: 43-49
  4. Sankar Gurumurthy, Shobha Vasudevan and J. A. Abraham. Automated Mapping of Pre-Computed Module-Level Test Sequences to Processor Instructions, International Test Conference (ITC) 2005:10-20
  5. Sankar Gurumurthy, Shobha Vasudevan and J. A. Abraham. Automated functional propagation of module level test responses, International Test Conference (ITC) 2006: 1-9
  6. Shobha Vasudevan, Vinod Viswanath, J. A. Abraham, and Jiajin Tu . Sequential Equivalence Checking of System Level and RTL Descriptions using Effective Compare Points, Austin Conference of Integrated Systems and Circuits (ACISC) 2006.
  7. Vinod Viswanath, Shobha Vasudevan and J. A. Abraham. Dedicated Rewriting: Automatic Verification of Low Power Transformations in RTL, International Conference on VLSI Design (VLSI Design) 2009: 77-82
  8. Shobha Vasudevan, David Sheridan, Sanjay Patel, Bill Tuohy. GoldMine: Automatic generation of assertions using data mining and static analysis, Design Automation and Test in Europe (DATE) 2010:626-629
  9. Lingyi Liu and Shobha Vasudevan STAR: Generating Validation Inputs by Static Analysis of RTL, International High Level Design Validation and Test Workshop (HLDVT) 2009: 32-37
  10. Jayanand Asok Kumar and Shobha Vasudevan Automatic compositional reasoning for probabilistic model checking of hardware designs, International Conference on Quantitative Evaluation of Systems (QEST) 2010:
  11. Viraj Athavale, Jayanand Asok Kumar and Shobha Vasudevan A Scalable Approach for Throughput Estimation of Timing Speculation Designs, MWSCAS 2010
  12. Jayanand Asok Kumar and Shobha Vasudevan Statistical Guarantees of Performance for MIMO Designs, International Conference on Dependable Systems and Networks (DSN) 2010:
  13. Shobha Vasudevan: Coverage closure in SoC verification: Are we chasing a mirage? VLSI Test Symposium (VTS )2011
  14. Jayanand Asok Kumar and Shobha Vasudevan, Variation-Conscious Formal Timing Verification in RTL, International Conference on VLSI Design (VLSI Design) 2011:58-63
  15. Lingyi Liu, David Sheridan, William Tuohy, Shobha Vasudevan Towards coverage closure: Using GoldMine assertions for generating design validation stimulus, Design Automation and Test in Europe (DATE) 2011: 173-178
  16. Lingyi Liu and Shobha Vasudevan Efficient validation input generation in RTL using hybridized source code analysis, Design Automation and Test in Europe (DATE) 2011: 1596-1601
  17. Lingyi Liu, David Sheridan, Viraj Athavale, Shobha Vasudevan: Automatic generation of assertions from system level design using data mining, , International Conference on Formal Methods and Models for Codesign (MEMOCODE ) 2011: 191-200
  18. Jayanand Asok Kumar Lingyi Liu and Shobha Vasudevan, Scaling Probabilistic Timing Verification of Hardware Using Abstractions in Design Source Code, Formal Methods in Computer Aided Design, (FMCAD) 2011: 196-205
  19. Shobha Vasudevan, GoldMine: Automatic assertion generation using data mining and static analysis, Design and Verification Conference, (DVCON) 2011
  20. Parth Sagdeo, Viraj Athavale Sumant Kowshik and Shobha Vasudevan PRECIS: Inferring Invariants using Program Path Guided Clustering, International Conference on Automated Software Engineering (ASE) 2011: 532-535
  21. Hyungsul Kim, David Sheridan, Sungjin Im, Shobha Vasudevan, Tarek Abdelzaher and Jiawei Han, Signature Pattern Covering via Local Greedy Algorithm and Pattern Shrink, , 2011 International Conference on Data Mining ( ICDM) 2011: 330-339
  22. Jayanand Asok Kumar and Shobha Vasudevan: Verifying dynamic power management schemes using statistical model checking. Asia South Pacific Design Automation Conference (ASP-DAC) 2012: 579-584
  23. Jayanand Asok Kumar, Kenneth M Butler, Heesoo Kim and Shobha Vasudevan, Early prediction of NBTI effects using RTL source code analysis, Design Automation Conference (DAC) 2012: 808-813
  24. Seyed Nematollah Ahmadyan, Jayanand Asok Kumar and Shobha Vasudevan, Goal-oriented stimulus generation for analog circuits, Design Automation Conference (DAC) 2012: 1018-1023
  25. Viraj Athavale,Sam Hertz, Darshan Jetly, Vijay Ganesan, Jim Krysl and Shobha Vasudevan, Using static analysis for coverage extraction from emulation/prototyping platforms, IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, (CODES+ISSS) 2012: 207-214
  26. Lingyi Liu, Chen Hsuan Lin and Shobha Vasudevan, Word Level Feature Discovery to Enhance Quality of Assertion Mining, International Conference on Computer Aided Design ( ICCAD) 2012: 210-217
  27. Seyed Nematollah Ahmadyan and Shobha Vasudevan, Reachability Analysis of Nonlinear Analysis through Iterative Reachable Set Reduction, Design Automation and Test in Europe (DATE) 2013: 1436-1441
  28. Seyed Nematollah Ahmadyan and Shobha Vasudevan, Runtime Verification of Nonlinear Analog Circuits Using Incremental Time-Augmented RRT Algorithm, Design Automation and Test in Europe (DATE) 2013: 21-26
  29. Chen-Hsuan Lin, Lingyi Liu and Shobha Vasudevan, Generating concise assertions with complete coverage, ACM Great Lakes Symposium on VLSI (GLSVLSI) 2013, pp 185-190
  30. Lingyi Liu, Shobha Vasudevan, Scaling RTL property checking using feasible path analysisand decomposition, ACM Great Lakes Symposium on VLSI (GLSVLSI) 2013, pp 173-178
  31. Parth Sagdeo, Nicholas Ewalt, Debjit Pal and Shobha Vasudevan, Using Automatically Generated Invariants for Regression Testing and Bug Localization, International Conference on Automated Software Engineering (ASE) 2013: 634-639
  32. Seyed Nematollah Ahmadyan and Shobha Vasudevan, Efficient Stochastic SAT Solving Using Random Graphs. Invited paper in Workshop for Constraints in Formal Verification (CFV), 2013
  33. Lingyi Liu, Xuanyu Zhong, Xiaotao Chen and Shobha Vasudevan, Diagnosing Root Causes of System Level Performance Violations, International Conference on Computer Aided Design (ICCAD) 2013: 295-302
  34. David Sheridan, Lingyi Liu, Hyungsul Kim and Shobha Vasudevan , A Coverage Guided Mining Approach for Automatic Generation of Succinct Assertions. In Proceedings of International Conference on VLSI Design (VLSI Design) 2014 . Best paper award.
  35. Viraj Athavale, Sai Ma, Samuel Hertz and Shobha Vasudevan, Code Coverage of Assertions Using RTL Source Code Analysis. Design Automation Conference (DAC) 2014. Best paper award.
  36. Seyed Nematollah Ahmadyan, Shobha Vasudevan, Eli Chiprout, Chenjie Gu and Suriyaprakash Natarajan, Fast Eye Diagram Analysis for High-Speed CMOS Circuits. To appear in Design Automation and Test in Europe (DATE) 2015.

Book chapter/Theses

  1. Shobha Vasudevan and Jacob A. Abraham. Static Program Transformations for Efficient Software Model Checking, Book chapter in World Congress of Computers (WCC), 2004. IFIP Congress Topical Sessions 2004: 257-282
  2. Shobha Vasudevan. Automatic Verification of Arithmetic Circuits in RTL Using Term Rewriting Systems, Masters Thesis, December 2003, The University of Texas at Austin.
  3. Shobha Vasudevan. Static analysis of high level descriptions in hardware for taming verification complexity, PhD Thesis, May 2008, The University of Texas at Austin.