In Stanford for 2017
I will be visiting the CS department at Stanford University in 2017. I am visiting Prof Subhashish Mitra and interacting with his wonderful group of students with a view to fostering collaborations.
Take a bow, Adel!
Seyed Nematollah Ahmadyan (Adel) defended his thesis in front of a distinguished committee (Rob Rutenbar, Xin Li, Sayan Mitra, Martin Wong) with flying colors! What started as an analog verification and testing PhD, morphed into an optimization PhD by the time we were done! Adel's DUPLEX algorithm is a randomized tree based search/sampling algorithm that can create directed analog stimulus, the worst case "eye" diagram and the shortest length analog tests. It is also one of the few numerical algorithms to solve functional optimization problems and can beat state-of-the-art non-convex optimization algorithms as well! Adel will be taking his optimization expertise to SnapChat starting January 2017.
Debjit Pal was selected for IEEE-CEDA SVDTC student research award for 2017. His research on post-Silicon signal tracing for debug of SoCs was recognized.
I am on the TPC of DATE 2017. Please send us high quality submissions!
IBM Faculty partnership
Prof. Shobha Vasudevan awarded the IBM faculty partnership award 2017 for post Silicon validation of many core systems
Associate Editor, IEEE TCAD
Prof Shobha Vasudevan appointed as Associate Editor of IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)
Congratulations Jiayi Duan!
Jiayi Duan from our group finished a master's thesis on "Feature Engineering for Detecting Security Compromises in Enterprise Log Data". He used a creative method based on Fourier Transforms to get more than 70% increased malicious recall on real enterprise log data. He will be working on machine learning problems in Amazon Inc. starting July 2016.
Post-Si paper nominated for Best Paper award in ICCAD 2015
Watch out for our radical Post-Silicon validation paper in ICCAD 2015!
Our paper, "Can't see the forest for the trees: State restoration's limitations in selecting signals for post-silicon debug" systematically exposes the pitfalls of the state restoration ratio (SRR) signal selection methodologies of the past decade. It takes a first step in the direction of thinking differently about post-Silicon signal selection and opens it up for potentially better solutions.
Eye diagram analysis paper nominated for Best Paper
Our paper, Fast Eye Diagram Analysis for High Speed CMOS Circuits was nominated for best paper at DATE 2015. It was one of 6 about 240 accepted papers. Congratulations to my student Seyed Nematollah (Adel) Ahmadyan! The paper was written in collaboration with Intel and presents a powerful method to explore the analog/mixed signal design space. This proposes an alternative for Monte Carlo simulations. Has applications in embedded systems like automotives and biomedical devices that use a wide variety of analog and mixed signal chips.
Keynote speech at DATE workshop
Shobha Vasudevan gave a keynote address at the vibrant DUHDE workshop colocated with DATE 2015.
IEEE Design and Test editorial board
Shobha Vasudevan named as one of the editors of IEEE Design and Test. Please submit good papers to this magazine with wide readership in the design community.
IEEE CEDA Early Career Award
Shobha Vasudevan named as the 2014 recipient of the IEEE Council of EDA Early Career Award.
Best Paper Award in DAC 2014
Best paper award in VLSI Design 2014
Our paper "A Coverage Guided mining Approach for Automatic Generation of Succint Assertions" was awarded the best paper award at the VLSI Design conference 2014. Yet another GoldMine victory! The authors are Shobha Vasudevan, Lingyi Liu, David Sheridan and Hyung Sul Kim. An article appeared on the ECE website on it.
Shobha Vasudevan named a recepient of 2014 Dean's award for excellence in research
Dean's award for excellence in research is awarded by the UIUC college of Engineering annually. Here is an article about the ECE professors who won the college awards this year.
Watch out for our paper at DAC 2014
"Code Coverage of Assertions Using RTL Source Code Analysis" by Viraj Athavale, Sai Ma, Sam Hertz and Shobha Vasudevan. This paper generates a code coverage metric for assertions using dynamic and static analysis techniques. Attend our presentation at DAC 2014!
System level assertion generation for performance and functionality
Automatic Generation of System Level Assertions from Transaction Level Models. Lingyi Liu and Shobha Vasudevan. Accepted. To appear in Journal of Electronic Testing: Theory and Applications (JETTA)
Our paper on invariant mining for debugging programs in ASE 2013
Parth Sagdeo et al's paper "Using Automatically Generated Invariants for Regression Testing and Bug Localization" introduces a novel bug localization methodology with PREAMBL, a predicate clustering and invariant guided tool. Invariants from PRECIS in ASE 2011 are used for software regression testing as well.
Watch our for our ICCAD 2013 paper on system level debug and diagnosis
Our paper "Diagnosing Root Causes of System Level Performance Violations" to be published in ICCAD 2013 uses a unique, data mining approach to pinpoint latency and throughput bottlenecks in system level designs. This problem was proposed by Huawei Technologies, and is a product of our collaboration with them.
Vasudevan's group has two papers in IEEE Transactions on CAD (TCAD) in May 2013
Our papers "Formal probabilistic timing verification in RTL" and "Mining Hardware Assertions With Guidance from Static Analysis" cover two diverse aspects of hardware verification. Read and enjoy!
The award is given by ACM SIGDA to one junior faculty member who displays outstanding potential as an educator and/or researcher in the field of EDA. Many thanks to my students and collaborators for their role in this recognition. Pictures of the award ceremony can be found here.