Shobha Vasudevan -- Assistant Professor UIUC

Shobha Vasudevan
Assistant Professor
Electrical and Computer Engineering
University of Illinois at Urbana-Champaign
260 Coordinated Sciences Laboratory (CSL)
Office: 217 333 8164
Email: shobhav AT [my university]

Research

I am interested in formal verification of hardware, SoC verification, model checking, term rewriting systems, system level equivalence checking, RTL verification and validation, multicore processor verification and analog verification.
I am looking for motivated graduate students to work with on exciting new research areas. Interested students may contact me by email or meet me in my office.

Publications

High Level Static Analysis of System Descriptions for Taming Verification Complexity, PhD Thesis, The University of Texas at Austin

Automatic Verification of Arithmetic circuits in RTL using Term Rewriting Systems, Master's thesis

Efficient Model Checking of hardware using Conditioned Slicing, Joint work with Allen Emerson and Jacob Abraham, AVOCS 2004. ENTCS proceedings of AVOCS 2004.

Static Program Transformation for Efficient Software Model Checking, Joint work with Jacob Abraham, book chapter in IFIP Congress Topical Sessions 2004

Improved Verification of Hardware Designs through Antecedent Conditioned Slicing, Joint work with Allen Emerson and Jacob Abraham, In International Journal on Software Tools for Technology Transfer (STTT), Feb 2007. Some notes on the implementation of the algorithm by Dr. Emerson.

Automated Mapping of Pre-Computed Module-Level Test Sequences to Processor Instructions, Joint work with Sankar Gurumurthy and Jacob Abraham, International Test Conference (ITC) 2005

Automatic Verification of Arithmetic Circuits using Stepwise Refinement of Term Rewriting Systems, Joint work with Vinod Viswanath, Robert Sumners and Jacob Abraham, accepted in IEEE Transactions on Computers

Automatic Decomposition for Sequential Equivalence Checking of System Level and RTL Descriptions, Joint work with Vinod Viswanath, Jacob Abraham and Jiajin Tu, MEMOCODE 2006

Automated functional propagation of module level test reponses, Joint work with Sankar Gurumurthy and Jacob Abraham, International Test Conference (ITC) 2006

Sequential Equivalence Checking of System Level and RTL Descriptions using Effective Compare Points, in ACISC 2006

Efficient Microprocessor Verification using Antecedent Conditioned Slicing, Joint work with Vinod Viswanath and Jacob Abraham, VLSI Design 2007

Sequential Equivalence Checking between System Level and RTL Descriptions, Design Automation for Embedded Systems, Springer US, 26.11.2008, vol. 12, no. 4, pp. 377-396

Microprocessor Verification using RT-Level Static Analysis Techniques, Submitted to IEEE Transactions on VLSI. This paper contains a revised antecedent conditioned slicing algorithm.

Dedicated Rewriting: Automatic Verification of Low Power Transformations in RTL, Joint work with Vinod Viswanath and Jacob Abraham, VLSI Design 2009

Education

Ph.D : Electrical and Computer Engineering, The University of Texas at Austin
MS :

Electrical and Computer Engineering,

The University of Texas at Austin
B.E : Computer Engineering, University of Mumbai, India.

Teaching

Spring 2008: Logic Design ECE462/CS462/MATH491

Formal Hardware/SoC Verification ECE598SV

Logic Design ECE462/CS462/MATH491